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/*!
 * @file ac780x_ckgen.c
 *
 * @brief This file provides all clock generator config functions.
 *
 */

/* ===========================================  Includes  =========================================== */
#include "ac780x_ckgen.h"

/* ============================================  Define  ============================================ */

/* ===========================================  Typedef  ============================================ */

/* ==========================================  Variables  =========================================== */
/* for SPM Event call back function */
static DeviceCallback_Type s_nmiCallback = NULL;

/* ====================================  Functions declaration  ===================================== */

/* ======================================  Functions define  ======================================== */
/*!
 * @brief Enable the module clock.
 *
 * @param[in] module: CKGEN_ClockType, value can be
 *                   - CLK_UART0
 *                   - CLK_UART1
 *                   - CLK_UART2
 *                   - CLK_SPI0
 *                   - CLK_SPI1
 *                   - CLK_I2C0
 *                   - CLK_I2C1
 *                   - CLK_PWDT0
 *                   - CLK_PWM0
 *                   - CLK_PWM1
 *                   - CLK_PWM2
 *                   - CLK_TIMER
 *                   - CLK_RTC
 *                   - CLK_DMA0
 *                   - CLK_GPIO
 *                   - CLK_WDG
 *                   - CLK_CRC
 *                   - CLK_EIO
 *                   - CLK_CAN0
 *                   - CLK_CAN1
 *                   - CLK_CTU
 *                   - CLK_ADC0
 *                   - CLK_ACMP0
 *                   - CLK_PWDT1
 * @param[in] enable: enable state
 *                   - ENABLE
 *                   - DISABLE
 * @return none
 */
void CKGEN_Enable(CKGEN_ClockType module, ACTION_Type enable)
{
    uint32_t moduleValue = (uint32_t)module;

    DEVICE_ASSERT(IS_CKGEN_CLOCK_PARA(module));
    if (moduleValue < 32U)
    {
        if (ENABLE == enable)
        {
            SET_BIT32(CKGEN->PERI_CLK_EN_0, (uint32_t)(1UL << moduleValue));
        }
        else
        {
            CLEAR_BIT32(CKGEN->PERI_CLK_EN_0, (uint32_t)(1UL << moduleValue));
        }
    }
    else if (moduleValue < (uint32_t)CLK_MODULE_NUM)
    {
        moduleValue -= 32U;
        if (ENABLE == enable)
        {
            SET_BIT32(CKGEN->PERI_CLK_EN_1, (uint32_t)(1UL << moduleValue));
        }
        else
        {
            CLEAR_BIT32(CKGEN->PERI_CLK_EN_1, (uint32_t)(1UL << moduleValue));
        }
    }
    else
    {
        /* do nothing */
    }
}

/*!
 * @brief Do soft reset for the module.
 *
 * @param[in] module: the module to do soft reset, value can be
 *                   - SRST_UART0
 *                   - SRST_UART1
 *                   - SRST_UART2
 *                   - SRST_SPI0
 *                   - SRST_SPI1
 *                   - SRST_I2C0
 *                   - SRST_I2C1
 *                   - SRST_PWDT0
 *                   - SRST_PWM0
 *                   - SRST_PWM1
 *                   - SRST_PWM2
 *                   - SRST_TIMER
 *                   - SRST_RTC
 *                   - SRST_DMA0
 *                   - SRST_GPIO
 *                   - SRST_WDG
 *                   - SRST_CRC
 *                   - SRST_EIO
 *                   - SRST_CAN0
 *                   - SRST_CAN1
 *                   - SRST_CTU
 *                   - SRST_ADC0
 *                   - SRST_ACMP0
 *                   - SRST_ANA_REG
 *                   - SRST_PWDT1
 * @param[in] active: active state
 *                   - ENABLE
 *                   - DISABLE
 * @return none
 */
void CKGEN_SoftReset(CKGEN_SoftResetType module, ACTION_Type active)
{
    uint32_t moduleValue = (uint32_t)module;

    DEVICE_ASSERT(IS_CKGEN_SOFT_RESET_PARA(module));
    if (moduleValue < 32U)
    {
        if (ENABLE == active)
        {
            SET_BIT32(CKGEN->PERI_SFT_RST0, (uint32_t)(1UL << moduleValue));
        }
        else
        {
            CLEAR_BIT32(CKGEN->PERI_SFT_RST0, (uint32_t)(1UL << moduleValue));
        }
    }
    else if (moduleValue < (uint32_t)SRST_MODULE_NUM)
    {
        moduleValue -= 32U;
        if (ENABLE == active)
        {
            SET_BIT32(CKGEN->PERI_SFT_RST1, (uint32_t)(1UL << moduleValue));
        }
        else
        {
            CLEAR_BIT32(CKGEN->PERI_SFT_RST1, (uint32_t)(1UL << moduleValue));
        }
    }
    else
    {
        /* do nothing */
    }
}

/*!
 * @brief Set the system clock source.
 *
 * @param[in] clockSource: system clock source, value can be
 *                        - SYSCLK_SRC_INTERNAL_OSC
 *                        - SYSCLK_SRC_PLL_OUTPUT
 *                        - SYSCLK_SRC_EXTERNAL_OSC
 * @return none
 */
void CKGEN_SetSysclkSrc(SYSTEM_ClockSourceType clockSource)
{
    DEVICE_ASSERT(IS_CLOCK_SOURCE_PARA(clockSource));
    MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_SYSCLK_SEL_Msk, CKGEN_CTRL_SYSCLK_SEL_Pos, (uint32_t)clockSource);
}

/*!
 * @brief Set the sysclck divider.
 *
 * @param[in] div: system clock divider set, value can be
 *                - SYSCLK_DIVIDER_1
 *                - SYSCLK_DIVIDER_2
 *                - SYSCLK_DIVIDER_3
 *                - SYSCLK_DIVIDER_4
 * @return none
 */
void CKGEN_SetSysclkDiv(SYSCLK_DividerType div)
{
    DEVICE_ASSERT(IS_SYSCLK_DIVIDER_PARA(div));
    MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_SYSCLK_DIV_Msk, CKGEN_CTRL_SYSCLK_DIV_Pos, (uint32_t)div);
}

/*!
 * @brief Set the APB clock divider.
 *
 * @param[in] div: apb clock divider set, value can be
 *                - APBCLK_DIVIDER_1
 *                - APBCLK_DIVIDER_2
 *                - APBCLK_DIVIDER_3
 *                - APBCLK_DIVIDER_4
 * @return none
 */
void CKGEN_SetAPBClockDivider(APBCLK_DividerType div)
{
    DEVICE_ASSERT(IS_APBCLK_DIVIDER_PARA(div));
    MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_APBCLK_DIV_Msk, CKGEN_CTRL_APBCLK_DIV_Pos, (uint32_t)div);
}

/*!
 * @brief Enable/disable the XOSC monitor.
 *
 * @param[in] enable: enable state
 *                   - ENABLE
 *                   - DISABLE
 * @return none
 */
void CKGEN_EnableXOSCMonitor(ACTION_Type enable)
{
    MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_XOSC_MON_EN_Msk, CKGEN_CTRL_XOSC_MON_EN_Pos, (uint32_t)enable);
}

/*!
 * @brief Set the PLL reference.
 *
 * @param[in] ref: set PLL reference clock, value can be
 *                - PLL_REF_INTERNAL_OSC(8M)
 *                - PLL_REF_EXTERNAL_OSC
 * @return none
 */
void CKGEN_SetPLLReference(PLL_ReferenceType ref)
{
    DEVICE_ASSERT(IS_PLL_REFERENCE_PARA(ref));
    MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_PLL_REF_SEL_Msk, CKGEN_CTRL_PLL_REF_SEL_Pos, (uint32_t)ref);
}

/*!
 * @brief Set the PLL previous divider.
 *
 * @param[in] div: set pll PREDIV, value can be
 *                - PLL_PREDIV_1
 *                - PLL_PREDIV_2
 *                - PLL_PREDIV_4
 * @return none
 */
void CKGEN_SetPllPrevDiv(PLL_PreDivType div)
{
    DEVICE_ASSERT(IS_PLL_PREDIV_PARA(div));
    MODIFY_REG32(ANA->SYSPLL1_CFG0, ANA_SYSPLL1_CFG0_SYSPLL1_PREDIV_Msk, ANA_SYSPLL1_CFG0_SYSPLL1_PREDIV_Pos, (uint32_t)div);
}

/*!
 * @brief Set the PLL post divider.
 *
 * @param[in] div: set pll post-divider, value can be
 *                - PLL_POSDIV_1
 *                - PLL_POSDIV_2
 *                - PLL_POSDIV_4
 *                ...
 *                - PLL_POSDIV_62
 * @return none
 */
void CKGEN_SetPllPostDiv(PLL_PosDivType div)
{
    DEVICE_ASSERT(IS_PLL_POSDIV_PARA(div));
    MODIFY_REG32(ANA->SYSPLL1_CFG0, ANA_SYSPLL1_CFG0_SYSPLL1_POSDIV_Msk, ANA_SYSPLL1_CFG0_SYSPLL1_POSDIV_Pos, (uint32_t)div);
}

/*!
 * @brief Set the PLL feedback divider.
 *
 * @param[in] div: set pll FBKDIV, value can be 6 to 255
 * @return none
 */
void CKGEN_SetPllFeedbackDiv(uint8_t div)
{
    MODIFY_REG32(ANA->SYSPLL1_CFG0, ANA_SYSPLL1_CFG0_SYSPLL1_FBKDIV_Msk, ANA_SYSPLL1_CFG0_SYSPLL1_FBKDIV_Pos, (uint32_t)div);
}

/*!
 * @brief Set the CAN function clock.
 *
 * @param[in] canIndex: CAN0/1
 * @param[in] sel: can clock source select, value can be
 *                - CAN_CLK_SEL_EXTERNAL_OSC
 *                - CAN_CLK_SEL_AHB
 * @return none
 */
void CKGEN_SetCANClock(uint8_t canIndex, CAN_ClockSelectType sel)
{
    DEVICE_ASSERT(IS_CAN_CLOCK_SELECT_PARA(sel));

    if (0U == canIndex)
    {
        MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_CAN0_CLK_SEL_Msk, CKGEN_CTRL_CAN0_CLK_SEL_Pos, (uint32_t)sel);
    }
    else if (1U == canIndex)
    {
        MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_CAN1_CLK_SEL_Msk, CKGEN_CTRL_CAN1_CLK_SEL_Pos, (uint32_t)sel);
    }
}

/*!
 * @brief Set the CAN time stamp clock divider.
 *
 * @param[in] canIndex: CAN0/1
 * @param[in] divider: CAN time stamp clock divider, value can be
 *                - CAN_TIME_CLK_DIVIDER_8
 *                - CAN_TIME_CLK_DIVIDER_16
 *                - CAN_TIME_CLK_DIVIDER_24
 *                - CAN_TIME_CLK_DIVIDER_48
 * @return none
 */
void CKGEN_SetCANTimeDivider(uint8_t canIndex, CAN_TimeClockDividerType divider)
{
    DEVICE_ASSERT(IS_CAN_TIMECLOCK_DIVIDER_PARA(divider));

    if (0U == canIndex)
    {
        MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_CAN0_TIMCLK_DIV_Msk, CKGEN_CTRL_CAN0_TIMCLK_DIV_Pos, (uint32_t)divider);
    }
    else if (1U == canIndex)
    {
        MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_CAN1_TIMCLK_DIV_Msk, CKGEN_CTRL_CAN1_TIMCLK_DIV_Pos, (uint32_t)divider);
    }
}

/*!
 * @brief Set the clock output.
 *
 * @param[in] enable: enable state
 *                   - ENABLE
 *                   - DISABLE
 * @param[in] sel: clock output select, value can be
 *                - CKGEN_CLKOUT_SEL_HSI
 *                - CKGEN_CLKOUT_SEL_HSE
 *                - CKGEN_CLKOUT_SEL_PLL
 *                - CKGEN_CLKOUT_SEL_SYS
 * @param[in] div: clock output divider, value can be
 *                - CKGEN_CLKOUT_DIV_1
 *                - CKGEN_CLKOUT_DIV_2
 *                - CKGEN_CLKOUT_DIV_4
 *                - CKGEN_CLKOUT_DIV_8
 * @return none
 */
void CKGEN_SetClockOut(ACTION_Type enable, CKGEN_ClkOutSelType sel, CKGEN_ClkOutDivType div)
{
    DEVICE_ASSERT(IS_CLKOUT_SEL_PARA(sel));
    DEVICE_ASSERT(IS_CLKOUT_DIV_PARA(div));

    MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_CLKOUT_DIV_Msk, CKGEN_CTRL_CLKOUT_DIV_Pos, (uint32_t)div);
    MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_CLKOUT_SEL_Msk, CKGEN_CTRL_CLKOUT_SEL_Pos, (uint32_t)sel);
    MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_CLKOUT_EN_Msk, CKGEN_CTRL_CLKOUT_EN_Pos, (uint32_t)enable);
}

/*!
 * @brief Set NMI IRQHandler callback function.
 *
 * @param[in] eventFunc: the pointer of the NMI call back function
 * @return none
 */
void NMI_SetCallback(const DeviceCallback_Type eventFunc)
{
    s_nmiCallback = eventFunc;
}

/*!
 * @brief Override the NMI_Handler.
 *
 * @param[in] none
 * @return none
 */
void NMI_Handler(void)
{
    uint32_t wakeupStatus = SPM_GetModuleWakeupSourceFlag();

    /* check if nmi_b pad triggle nmi interrupt */
    if (wakeupStatus & SPM_WAKEUP_IRQ_STATUS_NMI_Msk)
    {
        /* write 1 clear NMI IRQ flag */
        SET_BIT32(SPM->WAKEUP_IRQ_STATUS, SPM_WAKEUP_IRQ_STATUS_NMI_Msk);
        if (s_nmiCallback != NULL)
        {
            s_nmiCallback(NULL, wakeupStatus, 0U);
        }
    }

    /* check if xosc loss or pll unlock triggle nmi interrupt */
    if (CKGEN->RESET_STATUS & (CKGEN_RESET_STATUS_XOSC_LOSS_RST_STATUS_Msk | CKGEN_RESET_STATUS_PLL_UNLOCK_RST_STATUS_Msk))
    {
        /* clear all reset status to prevent always run in nmi_handler */
        SET_BIT32(CKGEN->RESET_STATUS, CKGEN_RESET_STATUS_CLR_RESET_STATUS_Msk);

#if CKGEN_AUTO_CHANGE_CLK
        #if (AC780X_CLOCK_SRC == IC_CLOCK_SRC_HSE_PLL)
        /* change clock source to internal clock */
        CKGEN_SetSysclkSrc(SYSCLK_SRC_INTERNAL_OSC);
        (void)SPM_EnablePLL(DISABLE);
        CKGEN_SetPLLReference(PLL_REF_INTERNAL_OSC);  /* change pll reference to hsi 8M */
        CKGEN_SetPllPrevDiv(PLL_PREDIV_1);
        CKGEN_SetPllPostDiv(PLL_POSDIV_8);
        #ifndef PLL_CONFIG_72M
        CKGEN_SetPllFeedbackDiv(64U);
        #else
        CKGEN_SetPllFeedbackDiv(72U);
        #endif
        if (SPM_EnablePLL(ENABLE) == SUCCESS)
        {
            CKGEN_SetSysclkSrc(SYSCLK_SRC_PLL_OUTPUT);  /* auto change system clock to pll output */
        }
        #else
        /* change clock source to internal clock */
        CKGEN_SetSysclkSrc(SYSCLK_SRC_INTERNAL_OSC);
        #endif
#endif
    }
}

/* =============================================  EOF  ============================================== */
